The disclosed subject matter relates generally to semiconductor devices and, more particularly, to the modeling of gate transconductance of a transistor device using a sub-circuit transistor model.
Compact models of metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in simulations of integrated circuits. Conventional compact models, such as a Berkeley Short-Channel IGFET Model (BSIM) or a Berkeley Short-Channel IGFET Model for Silicon-on-insulator devices (BSIMSOI), have been primarily employed to model (or capture) transistor properties, such as drive current, IDEFF, for digital circuits. To implement the transistor model, a reference transistor model is defined. The modeling system uses selected data (e.g., current-voltage (IV) operational characteristics) taken from an actual transistor and loads that data into a software modeling program. Parameters of the reference transistor model are then varied to attempt to match the modeled operational characteristics with the corresponding operational characteristics of the actual transistor.
Compact transistor models do not typically incorporate the breadth of parameters sufficient to accurately model transistor properties for analog circuits. One such analog parameter that is not accurately incorporated into the compact models is gate transconductance (gm) in a low voltage regime (i.e., gate voltage close to the threshold voltage of the transistor). Furthermore, fabricated transistors are subject to process induced variations that cannot be controlled. For example, a series of actual transistors may have slightly different channel lengths, layer thicknesses, threshold voltages, etc., causing differences in actual operating characteristics from transistor to transistor. Consequently, it is useful to build these variations into the transistor model to allow the prediction of how the fabricated transistor will perform with these random variations. Simulations of advanced circuits require that the systemic and random variations in transistor properties be correctly modeled. Given the lack of parameters to accurately model gm, it is very difficult to create a model that can simultaneously capture both variations in gm and variations in the digital properties (such as IDEFF) simultaneously.
One approach to modeling gm involves using the parameters included in the compact models, such as carrier mobility, gate oxide thickness, and gate length, to model gm and variations in gm. However, the digital properties (such as IDEFF) of the transistor are usually sensitive to these parameters. Therefore, it is difficult to employ these parameters to model gm and variations in gm without sacrificing the accuracy of the modeling of the digital properties.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.